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1. risc_dbg_uart risc_dbg_uart Public

   SystemVerilog 1

2. JTAG_to_UART JTAG_to_UART Public

   C++

3. Streaming-Trace-Buffer Streaming-Trace-Buffer Public

   SystemVerilog

4. sc-dpi sc-dpi Public

   Serial console direct programming interface (DPI) for Verilator

   C++

5. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog

6. VivadoMakefileTemplate VivadoMakefileTemplate Public

   Template project for automating building VHDL projects using Vivado and GNU Make.

   Tcl