ASML

Modern chips rely on a range of materials that not only make up the semiconductor die itself, but also play critical roles in the packaging that shields them and connects them to the outside world. Here are three materials that play a key role in both the microchip circuitry and the packaging that protects it: 💪 Silicon is the foundation that chips are built on because its semiconducting properties are behind transistors’ current-switching abilities. It’s also used for large-area substrates, or interposers, in 2.5D and 3D advanced packaging. ⏳ Silicon dioxide is used to form insulating layers in microchip structures. And, because of its thermal and mechanical properties, it’s also often a primary component of the epoxy molding compound used to encapsulate chips. 🟠 Copper is used for the interconnects that serve as a chip’s wiring, carrying electrical signals to and from transistors. Its electrical and mechanical properties, valued within chips, also lead to its widespread use for chip packaging connections. Together, these essential materials help ensure modern devices meet the demands of today’s technology landscape.

The introduction of extreme ultraviolet (EUV) lithography was a major leap forward for advanced chipmaking. But as chipmakers keep pushing for smaller, more powerful and more energy-efficient chips, the industry needs to keep asking: What comes next? That’s where High NA EUV comes in. It’s an evolution of our EUV technology that required years of innovation to deliver the next step in shrink and patterning performance. So what did we change in High NA EUV? Swipe through to learn the difference.

With continued shrink becoming more complex, chipmakers are pioneering new ways to improve chip performance. A key enabler of their innovation? Wafer bonding. By splitting device architectures over multiple silicon wafers and then bonding them together, chipmakers can enable more efficient power delivery, better signals and faster data flows. But implementing this kind of 3D integration also changes the demands of chip manufacturing. Here are 3 challenges chipmakers face when they use wafer bonding: 🔬 Overlay: Bonding wafers causes significant distortion and warping that need to be corrected for when the next layer is patterned on the bonded structure. 🎯 Alignment: To position bonded wafers for patterning, lithography systems have to detect alignment markings buried deep under existing layers. 🏭 Yield: Bonding increases the rate of patterning defects that can stop chips from working, causing lower yields. Tackling these challenges is key to maximizing throughput so chip manufacturing stays cost-efficient and chipmakers can keep innovating to push chip technology to the next level.

Understanding how to precisely print microchip patterns starts long before high-volume manufacturing. During R&D, chipmakers use computational lithography, optical metrology and e-beam inspection to understand how a chip design will translate onto a wafer – and how to get a lithography system to print that pattern as accurately as possible. By integrating these tools with lithography systems through holistic lithography, ASML helps chipmakers solve patterning challenges faster and lay the groundwork for printing more good chips per wafer in volume production.

New chip architectures and functionalities create exciting opportunities – but they also introduce manufacturing risk. Optimizing the process of ramping up from R&D to volume manufacturing helps chipmakers reduce that risk. Swipe to learn more about how holistic lithography enables them to move from innovation to volume production faster and more efficiently. 🏭

What do fundamental particles have to do with making microchips? Photons and electrons are at the heart of modern chip manufacturing, and their wave-like properties are key to achieving the accuracy and reliability needed to power everything from smartphones to supercomputers. Dive in to learn about the role each kind of particle plays in the process.

The first major components of our TWINSCAN EXE:5200B High NA EUV system have arrived at NY Creates’ Albany NanoTech Complex in the United States. 🚀 This is an important step toward bringing next-generation lithography capabilities into a shared R&D environment in the US. Once operational, the High NA EUV Lithography Center will give industry and academic partners access to advanced imaging capabilities that support increasingly complex device architectures and the semiconductor industry’s continued scaling roadmap. Installation will continue throughout 2026, with the system expected to begin supporting R&D activities in early 2027. We’re proud to work with NY Creates and its partners as this new capability takes shape in Albany.

Making chips more powerful means printing ever-smaller, more complex patterns – and doing it reliably, wafer after wafer. That challenge gets harder with every new generation of chip technology. To help chipmakers meet the most demanding patterning requirements, ASML developed holistic lithography: the integration of computational modeling, optical measurement and e-beam inspection with our lithography systems. The result? Deeper insight, faster optimization and greater control across the chipmaking process. This is how we help customers move from design to production quickly and manufacture their chips at the right cost.

High NA EUV has reached a new readiness milestone. 🎉 Intel Foundry has entered high-volume manufacturing for a subset of Intel® Core™ Ultra Series 3 processors, using ASML's High NA EUV technology on the Intel 18A process. This marks an important step in demonstrating High NA EUV readiness in a production environment. Developed to support semiconductor scaling in the 2 nm era and beyond, High NA EUV enables more precise patterning for advanced chip manufacturing. This milestone reflects decades of collaboration between Intel and ASML and helps pave the way for future adoption of the technology.

🚨 BREAKING: We just reported our Q2 2026 financial results! 📈 Our Q2 2026 total net sales were €9.3 billion. It was a very good quarter as we executed against strong demand across our product portfolio. 🤝 “Ongoing AI-related investments and continued progress in AI technologies are driving demand for advanced Logic and Memory chips, further strengthening the semiconductor industry's growth outlook,” ASML President and CEO Christophe Fouquet said. “Our customers, in turn, continue to accelerate their capacity expansion plans. This is translating into customer commitments across our product portfolio, providing ASML with increased visibility into longer-term demand. Our order intake remained extremely strong in the first half of the year.” ⚙️ “Based on this momentum, we are planning to add 30% to our 2026 0.33 NA EUV capacity of around 65 for 2027, and we are investigating to increase capacity with another 30% for 2028. Similarly, we plan to add 30% to our 2026 DUV immersion capacity of around 130 for 2027, and we are investigating to increase capacity with another 30% in 2028. In addition, we are continuing to significantly expand our upgrade portfolio.” ➡️ We expect third-quarter 2026 total net sales between €11.0 billion and €12.0 billion. We expect R&D costs of around €1.2 billion and SG&A costs of around €0.4 billion. 📊 "Given the business dynamics discussed above, we now expect total net sales for 2026 to be between €43 billion and €45 billion, with a gross margin between 54% and 56%,” Fouquet said.