CWE - CWE-1281: Sequence of Processor Instructions Leads to Unexpected Behavior (4.16)

Weakness ID: 1281

Vulnerability Mapping: ALLOWED This CWE ID may be used to map to real-world vulnerabilities
Abstraction: Base Base - a weakness that is still mostly independent of a resource or technology, but with sufficient details to provide specific methods for detection and prevention. Base level weaknesses typically describe issues in terms of 2 or 3 of the following dimensions: behavior, property, technology, language, and resource.

View customized information:

For users who are interested in more notional aspects of a weakness. Example: educators, technical writers, and project/program managers. For users who are concerned with the practical application and details about the nature of a weakness and how to prevent it from happening. Example: tool developers, security researchers, pen-testers, incident response analysts. For users who are mapping an issue to CWE/CAPEC IDs, i.e., finding the most appropriate CWE for a specific issue (e.g., a CVE record). Example: tool developers, security researchers. For users who wish to see all available information for the CWE/CAPEC entry. For users who want to customize what details are displayed.

Description

Specific combinations of processor instructions lead to undesirable behavior such as locking the processor until a hard reset performed.

Extended Description

If the instruction set architecture (ISA) and processor logic are not designed carefully and tested thoroughly, certain combinations of instructions may lead to locking the processor or other unexpected and undesirable behavior. Upon encountering unimplemented instruction opcodes or illegal instruction operands, the processor should throw an exception and carry on without negatively impacting security. However, specific combinations of legal and illegal instructions may cause unexpected behavior with security implications such as allowing unprivileged programs to completely lock the CPU.

Common Consequences

This table specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.

Scope	Impact	Likelihood
Integrity Availability	Technical Impact: Varies by Context

Potential Mitigations

Phase: Testing

Implement a rigorous testing strategy that incorporates randomization to explore instruction sequences that are unlikely to appear in normal workloads in order to identify halt and catch fire instruction sequences.

Phase: Patching and Maintenance

Patch operating system to avoid running Halt and Catch Fire type sequences or to mitigate the damage caused by unexpected behavior. See [REF-1108].

Relationships

This table shows the weaknesses and high level categories that are related to this weakness. These relationships are defined as ChildOf, ParentOf, MemberOf and give insight to similar items that may exist at higher and lower levels of abstraction. In addition, relationships such as PeerOf and CanAlsoBe are defined to show similar weaknesses that the user may want to explore.

Relevant to the view "Research Concepts" (CWE-1000)

Nature	Type	ID	Name
ChildOf	Pillar - a weakness that is the most abstract type of weakness and represents a theme for all class/base/variant weaknesses related to it. A Pillar is different from a Category as a Pillar is still technically a type of weakness that describes a mistake, while a Category represents a common characteristic used to group related things.	691	Insufficient Control Flow Management

Relevant to the view "Hardware Design" (CWE-1194)

Nature	Type	ID	Name
MemberOf	Category - a CWE entry that contains a set of other entries that share a common characteristic.	1201	Core and Compute Issues

Modes Of Introduction

The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.

Phase	Note
Architecture and Design	Unexpected behavior from certain instruction combinations can arise from bugs in the ISA
Implementation	Unexpected behavior from certain instruction combinations can arise because of implementation details such as speculative execution, caching etc.

Applicable Platforms

This listing shows possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.

Languages

Class: Not Language-Specific (Undetermined Prevalence)

Operating Systems

Class: Not OS-Specific (Undetermined Prevalence)

Architectures

Class: Not Architecture-Specific (Undetermined Prevalence)

Technologies

Class: Not Technology-Specific (Undetermined Prevalence)

Processor Hardware (Undetermined Prevalence)

Demonstrative Examples

Example 1

The Pentium F00F bug is a real-world example of how a sequence of instructions can lock a processor. The "cmpxchg8b" instruction compares contents of registers with a memory location. The operand is expected to be a memory location, but in the bad code snippet it is the eax register. Because the specified operand is illegal, an exception is generated, which is the correct behavior and not a security issue in itself. However, when prefixed with the "lock" instruction, the processor deadlocks because locked memory transactions require a read and write pair of transactions to occur before the lock on the memory bus is released. The exception causes a read to occur but there is no corresponding write, as there would have been if a legal operand had been supplied to the cmpxchg8b instruction. [REF-1331]

(bad code)

Example Language: x86 Assembly

lock cmpxchg8b eax

Example 2

The Cyrix Coma bug was capable of trapping a Cyrix 6x86, 6x86L, or 6x86MX processor in an infinite loop. An infinite loop on a processor is not necessarily an issue on its own, as interrupts could stop the loop. However, on select Cyrix processors, the x86 Assembly 'xchg' instruction was designed to prevent interrupts. On these processors, if the loop was such that a new 'xchg' instruction entered the instruction pipeline before the previous one exited, the processor would become deadlocked. [REF-1323]

Example 3

The Motorola MC6800 microprocessor contained the first documented instance of a Halt and Catch Fire instruction - an instruction that causes the normal function of a processor to stop. If the MC6800 was given the opcode 0x9D or 0xDD, the processor would begin to read all memory very quickly, in sequence, and without executing any other instructions. This will cause the processor to become unresponsive to anything but a hard reset. [REF-1324]

Example 4

The example code is taken from the commit stage inside the processor core of the HACK@DAC'19 buggy CVA6 SoC [REF-1342]. To ensure the correct execution of atomic instructions, the CPU must guarantee atomicity: no other device overwrites the memory location between the atomic read starts and the atomic write finishes. Another device may overwrite the memory location only before the read operation or after the write operation, but never between them, and finally, the content will still be consistent.

Atomicity is especially critical when the variable to be modified is a mutex, counting semaphore, or similar piece of data that controls access to shared resources. Failure to ensure atomicity may result in two processors accessing a shared resource simultaneously, permanent lock-up, or similar disastrous behavior.

(bad code)

Example Language: Verilog

if (csr_exception_i.valid && csr_exception_i.cause[63] && commit_instr_i[0].fu != CSR) begin

exception_o = csr_exception_i;
exception_o.tval = commit_instr_i[0].ex.tval;

end

The above vulnerable code checks for CSR interrupts and gives them precedence over any other exception. However, the interrupts should not occur when the processor runs a series of atomic instructions. In the above vulnerable code, the required check must be included to ensure the processor is not in the middle of a series of atomic instructions.

Refrain from interrupting if the intention is to commit an atomic instruction that should not be interrupted. This can be done by adding a condition to check whether the current committing instruction is atomic. [REF-1343]

(good code)

Example Language: Verilog

if (csr_exception_i.valid && csr_exception_i.cause[63] && !amo_valid_commit_o && commit_instr_i[0].fu != CSR) begin

exception_o = csr_exception_i;
exception_o.tval = commit_instr_i[0].ex.tval;

end

Observed Examples

Reference	Description
CVE-2021-26339	A bug in AMD CPU's core logic allows a potential DoS by using a specific x86 instruction sequence to hang the processor
CVE-1999-1476	A bug in some Intel Pentium processors allow DoS (hang) via an invalid "CMPXCHG8B" instruction, causing a deadlock

Memberships

This MemberOf Relationships table shows additional CWE Categories and Views that reference this weakness as a member. This information is often useful in understanding where a weakness fits within the context of external information sources.

Nature	Type	ID	Name
MemberOf	Category - a CWE entry that contains a set of other entries that share a common characteristic.	1410	Comprehensive Categorization: Insufficient Control Flow Management

Vulnerability Mapping Notes

Usage: ALLOWED

(this CWE ID may be used to map to real-world vulnerabilities)

Reason: Acceptable-Use

Rationale:

This CWE entry is at the Base level of abstraction, which is a preferred level of abstraction for mapping to the root causes of vulnerabilities.

Comments:

Carefully read both the name and description to ensure that this mapping is an appropriate fit. Do not try to 'force' a mapping to a lower-level Base/Variant simply to comply with this preferred level of abstraction.

Related Attack Patterns

CAPEC-ID	Attack Pattern Name
CAPEC-212	Functionality Misuse

References

[REF-1094] Christopher Domas. "Breaking the x86 ISA". <https://github.com/xoreaxeaxeax/sandsifter/blob/master/references/domas_breaking_the_x86_isa_wp.pdf>.

[REF-1108] Intel Corporation. "Deep Dive: Retpoline: A Branch Target Injection Mitigation". <https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/overview.html>. URL validated: 2023-04-07.

[REF-1323] "Cyrix coma bug". Wikipedia. 2006-03-22. <https://en.wikipedia.org/wiki/Cyrix_coma_bug>.

[REF-1324] Gary Wheeler. "Undocumented M6800 Instructions". 1977-12. <https://spivey.oriel.ox.ac.uk/wiki/images-corner/1/1a/Undoc6800.pdf>. URL validated: 2023-04-20.

[REF-1331] Robert R. Collins. "The Pentium F00F Bug". 1998-05-01. <https://www.drdobbs.com/embedded-systems/the-pentium-f00f-bug/184410555>. URL validated: 2023-04-25.

[REF-1342] "Hackatdac19 commit_stage.sv". 2019. <https://github.com/HACK-EVENT/hackatdac19/blob/619e9fb0ef32ee1e01ad76b8732a156572c65700/src/commit_stage.sv#L287:L290>. URL validated: 2023-06-21.

[REF-1343] Florian Zaruba, Michael Schaffner, Stefan Mach and Andreas Traber. "commit_stage.sv". 2018. <https://github.com/openhwgroup/cva6/blob/7951802a0147aedb21e8f2f6dc1e1e9c4ee857a2/src/commit_stage.sv#L296:L301>. URL validated: 2023-06-21.

Content History

Submissions
Submission Date	Submitter	Organization
2020-05-15 (CWE 4.1, 2020-02-24)	Nicole Fern	Cycuity (originally submitted as Tortuga Logic)
2020-05-15 (CWE 4.1, 2020-02-24)
Contributions
Contribution Date	Contributor	Organization
2023-06-21	Shaza Zeitouni, Mohamadreza Rostami, Pouya Mahmoody, Ahmad-Reza Sadeghi	Technical University of Darmstadt
2023-06-21	suggested demonstrative example
2023-06-21	Rahul Kande, Chen Chen, Jeyavijayan Rajendran	Texas A&M University
2023-06-21	suggested demonstrative example
2023-06-21	Hareesh Khattri	Intel Corporation
2023-06-21	contributed to observed example
Modifications
Modification Date	Modifier	Organization
2020-08-20	CWE Content Team	MITRE
2020-08-20	updated Related_Attack_Patterns
2021-03-15	CWE Content Team	MITRE
2021-03-15	updated Potential_Mitigations
2021-07-20	CWE Content Team	MITRE
2021-07-20	updated Name, Observed_Examples
2022-10-13	CWE Content Team	MITRE
2022-10-13	updated Applicable_Platforms, Demonstrative_Examples
2023-04-27	CWE Content Team	MITRE
2023-04-27	updated Demonstrative_Examples, Description, References, Relationships
2023-06-29	CWE Content Team	MITRE
2023-06-29	updated Demonstrative_Examples, Mapping_Notes, References
2023-10-26	CWE Content Team	MITRE
2023-10-26	updated Demonstrative_Examples, Observed_Examples
Previous Entry Names
Change Date	Previous Entry Name
2021-07-20	Sequence of Processor Instructions Leads to Unexpected Behavior (Halt and Catch Fire)


	Site Map \| Terms of Use \| Manage Cookies \| Cookie Notice \| Privacy Policy \| Contact Us \| Use of the Common Weakness Enumeration (CWE™) and the associated references from this website are subject to the Terms of Use. CWE is sponsored by the U.S. Department of Homeland Security (DHS) Cybersecurity and Infrastructure Security Agency (CISA) and managed by the Homeland Security Systems Engineering and Development Institute (HSSEDI) which is operated by The MITRE Corporation (MITRE). Copyright © 2006–2024, The MITRE Corporation. CWE, CWSS, CWRAF, and the CWE logo are trademarks of The MITRE Corporation.

Common Weakness Enumeration

CWE-1281: Sequence of Processor Instructions Leads to Unexpected Behavior

Edit Custom Filter